SD16730
Characteristics
Symbol
Test conditions
CLK－OUTn , LATCH = “H”,
ENABLE =“L”
Min.
Typ.
170
170
Max.
Unit
nS
T
-
340
pHL1
Propagation Delay Time (“H”
to “L”)
LATCH－OUTn , ENABLE =“L”
T
T
T
-
340
nS
pHL2
pHL3
pHL4
ENABLE －OUTn , LATCH =“H”
CLK－SERIAL OUT
-
4
170
7
340
-
nS
nS
nS
nS
uS
uS
Output Rise Time
t
-
-
-
-
40
40
-
85
70
-
150
150
5
or
Output Fall Time
t
of
Maximum CLOCK Rise Time
Maximum CLOCK Fall Time
t
r
t
-
-
5
f
PIN CONFIGURATION
GND
SERIAL-IN
CLOCK
LATCH
OUT0
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R-EXT
SERIAL-OUT
ENABLE
OUT7
OUT1
OUT6
OUT2
OUT5
OUT3
OUT4
PIN DESCRIPTIONS
Pin No.
Pin Name
GND
I/O
Description
1
2
--
I
Ground terminal
SERIAL-IN
CLOCK
Input terminal of a data shift register
Input terminal of a clock shift register
Input terminal of a data strobe
Output terminals
3
I
4
LATCH
I
5 ~ 12
13
14
15
16
~ OUT7
O
I
OUT0
ENABLE
Input terminal of output enable (low active)
output terminal of a data shift register
Input terminal of an external resistor
Supply voltage terminal
SERIAL-OUT
R-EXT
O
I
VDD
--
FUNCTION DESCRIPTION
In LED display application, SD16730 can maintain the current nearly no variations among different channels or
chips. The maximum current variation range is ±3% between channels and ±6% between chips.
This device has only one ground pin shared by signal, output sink current, and power ground. It is advisable to
pattern the ground layout with minimized inductance so that the switching noise induced by the input signals and
the output sink current would not cause chip malfunction. To prevent drivers’ outputs from damaging by
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.1
2008.11.16
Http://www.silan.com.cn
Page 4 of 12
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