Silan
Semiconductorsꢀ
SC84502
ꢀ
(continued)
Parameter
Symbol
Condition
Min
0.8
0.8
1.5
Typ
--
Max Unit
Schmitt trigger input, Ipl=76µA
Comparator input, Ipl=80µA
Comparator input, Ipl=500µA
1.2
1.2
2.1
V
V
V
X1,X2,Y1,Y2 input current
Vpl
--
--
CLK, DATA positive-going
threshold voltage
Vt+
Vt-
--
--
3.2
1.2
--
--
3.8
1.9
V
V
CLK, DATA negative-going
threshold voltage
Low Input Voltage, Other Pins
High Input Voltage, Other Pins
L,M,R Input Current
Vail
Vaih
Imi
--
--
--
--
--
1.5
--
V
V
--
3.5
Pull Up Resistor, Vin=5V
16.6
50
µA
PS/2 mouse mode
Idc
Vprl
Iil
Vin = 0V
0.56
--
--
--
--
1.86
0.4
mA
V
DATA,CLK input Current
PS/2 mouse mode
Iprl = -2 mA
Vin = 0V
DATA,CLK low output Voltage
L,M,R,X1,X2,Y1,Y2
0
1.0
µA
Input Leakage Current
Note: All voltages in above table are compared with VSS.
All parameters in above table are tested under VDD=5V.
CLK & DATA output gates are open drains that connect to pull up resistors.
AC ELECTRICAL CHARACTERISTICS
( Tamb = 0 ~ 70°C)
Parameter
Oscillating Frequency
Symbol
Min
Typ
Max
Unit
kHz
ms
µs
Fosc
Tkd
34.3-10%
34.3
12
34.3+10%
Key Debounce
--
14.3
14.3
--
--
--
--
--
--
--
--
--
--
--
Rising Edge Crossed Width Fosc=35 kHz
Falling Edge Crossed Width Fosc=35 kHz
Mouse CLK Active Time
Tr
--
Tf
--
µs
Tmca
Tmci
Tmdc
Tsca
Tsci
Tsdc
Tscd
42.9
42.9
14.3
42.9
42.9
14.3
28.6
µs
Mouse CLK Inactive Time
--
µs
Time that Mouse Sample DATA from CLK rising Edge
System CLK Active Time
--
µs
--
µs
System CLK Inactive Time
--
µs
Time from DATA Transition to Falling Edge of CLK
Time from rising Edge of CLK to DATA Transition
Time to mouse Inhibit after the 11th CLK to
ensure mouse does not start another Transmission
--
µs
--
µs
Tpi
0
--
50
µs
Note: The AC timings are measured under using 35kHz system clock signal.
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
ꢀ
Rev: 1.0
2000.12.31
ꢀ
3
SILAN [ SILAN MICROELECTRONICS JOINT-STOCK ]
