SC7314
APPLICATION NOTES
1. I2c bus interface
2
Data transmission from microprocessor to the SC7314 and viceversa takes place through the 2 wiresCI BUS
interface, consisting of the two lines SDA and SCL(pull•up resistors to positive supply voltage must be
connected).
2.Data validity
As shown in Figure 17, the data of the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Fig. 17 Data Validity on the I2C BUS
3. Start and stop conditions
As shown in Figure 18, a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
SCL
I2C
//
BUS
SDA
//
start
stop
2
Fig. 18 Timing diagram of I C BUS
4. Byte format
Every byte transferred on the SDA line must obtain 8 bits. Each byte must be followed by the an acknowledge
bit. The MSB is transferred first.
5. Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse(see Figure 19). The peripheral (audioprocessor) that acknowledges has to pull•down (LOW) the SDA line
during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the reception of each
byte, otherwise the SDA line remain at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
REV:1.1
2007.09.25
Http: www.silan.com.cn
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