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SST39VF1601-90-4I-B3KE 参数 Datasheet PDF下载

SST39VF1601-90-4I-B3KE图片预览
型号: SST39VF1601-90-4I-B3KE
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 1MX16, 90ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, MO-210AB-1, TFBGA-48]
分类和应用: 内存集成电路闪存
文件页数/大小: 32 页 / 379 K
品牌: SILICON [ SILICON ]
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16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus  
SST39VF1601 / SST39VF3201 / SST39VF6401  
SST39VF1602 / SST39VF3202 / SST39VF6402  
Preliminary Specifications  
TABLE 12: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1  
Limits  
Symbol Parameter  
Min  
Max  
Units  
Test Conditions  
IDD  
Power Supply Current  
Address input=VILT/VIHT2, at f=5 MHz,  
VDD=VDD Max  
Read3  
18  
35  
20  
20  
mA  
mA  
µA  
CE#=VIL, OE#=WE#=VIH, all I/Os open  
CE#=WE#=VIL, OE#=VIH  
Program and Erase  
Standby VDD Current  
Auto Low Power  
ISB  
CE#=VIHC, VDD=VDD Max  
IALP  
µA  
CE#=VILC, VDD=VDD Max  
All inputs=VSS or VDD, WE#=VIHC  
ILI  
Input Leakage Current  
1
µA  
µA  
VIN=GND to VDD, VDD=VDD Max  
ILIW  
Input Leakage Current  
on WP# pin and RST#  
10  
WP#=GND to VDD or RST#=GND to VDD  
ILO  
Output Leakage Current  
Input Low Voltage  
10  
0.8  
0.3  
µA  
V
VOUT=GND to VDD, VDD=VDD Max  
VDD=VDD Min  
VIL  
VILC  
VIH  
Input Low Voltage (CMOS)  
Input High Voltage  
V
VDD=VDD Max  
0.7VDD  
V
VDD=VDD Max  
VIHC  
VOL  
VOH  
Input High Voltage (CMOS)  
Output Low Voltage  
VDD-0.3  
V
VDD=VDD Max  
0.2  
V
IOL=100 µA, VDD=VDD Min  
Output High Voltage  
VDD-0.2  
V
IOH=-100 µA, VDD=VDD Min  
T12.8 1223  
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C  
(room temperature), and VDD = 3V. Not 100% tested.  
2. See Figure 17  
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.  
TABLE 13: RECOMMENDED SYSTEM POWER-UP TIMINGS  
Symbol  
Parameter  
Minimum  
100  
Units  
µs  
1
TPU-READ  
Power-up to Read Operation  
Power-up to Program/Erase Operation  
1
TPU-WRITE  
100  
µs  
T13.0 1223  
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.  
TABLE 14: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)  
Parameter  
Description  
Test Condition  
VI/O = 0V  
Maximum  
1
CI/O  
I/O Pin Capacitance  
Input Capacitance  
12 pF  
6 pF  
1
CIN  
VIN = 0V  
T14.0 1223  
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.  
TABLE 15: RELIABILITY CHARACTERISTICS  
Symbol  
Parameter  
Endurance  
Data Retention  
Latch Up  
Minimum Specification  
Units  
Cycles  
Years  
mA  
Test Method  
1,2  
NEND  
10,000  
100  
JEDEC Standard A117  
JEDEC Standard A103  
JEDEC Standard 78  
1
TDR  
1
ILTH  
100 + IDD  
T15.2 1223  
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.  
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a  
higher minimum specification.  
©2003 Silicon Storage Technology, Inc.  
S71223-03-000  
11/03  
13