SiM3C1xx
4.3. Clocking
The SiM3C1xx devices have two system clocks: AHB and APB. The AHB clock services memory peripherals and
is derived from one of seven sources: the RTC0 Oscillator, the Low Frequency Oscillator, the Low Power Oscillator,
the divided Low Power Oscillator, the External Oscillator, and the PLL0 Oscillator. In addition, a divider for the AHB
clock provides flexible clock options for the device. The APB clock services data peripherals and is synchronized
with the AHB clock. The APB clock can be equal to the AHB clock (if AHB is less than or equal to 50 MHz) or set to
the AHB clock divided by two.
Clock Control allows the AHB and APB clocks to be turned off to unused peripherals to save system power. Any
registers in a peripheral with disabled clocks will be unable to be accessed until the clocks are enabled. Most
peripherals have clocks off by default after a power-on reset.
Clock Control
RTC0
Oscillator
RAM
DMA
LFOSC0
AHB clock
Flash
LPOSC0
AHB Clock
Divider
EMIF
PLL0 Registers
External
Oscillator
PBCFG and
PB0/1/2/3/4
USART0
USART1
UART0
APB clock
PLL0
Oscillator
APB Clock
Divider
Preliminary Rev. 0.8
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SILICON [ SILICON ]
