Si8430/31/35
Table 5. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
2.3
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
—
µA
L
2
Z
85
Output Impedance
O
I
V
= V
IH
2.0
2.0
—
µA
µA
Enable Input High Current
Enable Input Low Current
ENH
ENx
I
V
= V
IL
—
ENL
ENx
DC Supply Current (All inputs 0 V or at supply)
Si8430Ax, Bx and Si8435Bx
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.2
1.9
4.2
1.9
1.8
2.9
6.3
2.9
V
V
V
V
DD1
DD2
DD1
DD2
mA
mA
Si8431Ax, Bx
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
2.0
3.7
3.0
2.6
3.0
5.6
4.5
V
V
V
V
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8430Ax, Bx and Si8435Bx
—
—
2.7
2.2
4.1
3.3
V
V
DD1
DD2
mA
mA
Si8431Ax, Bx
—
—
2.8
2.7
4.2
4.1
V
V
DD1
DD2
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.5
SILICON [ SILICON ]
