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SI5XX-EVB 参数 Datasheet PDF下载

SI5XX-EVB图片预览
型号: SI5XX-EVB
PDF下载: 下载PDF文件 查看货源
内容描述: 评估板用于Si53X XOS和Si55X压控石英振荡器 [EVALUATION BOARD FOR Si53X XOS AND Si55X VCXOS]
分类和应用: 振荡器石英晶振压控振荡器
文件页数/大小: 8 页 / 232 K
品牌: SILICON [ SILICON ]
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Si5xx-EVB  
1.2. Voltage Control for VCXOs  
1. Functional Description  
The voltage control (V ) input of the Si55x device is  
C
The Si5xx-EVB provides access to all signals for  
configuring and operating the device. This board allows  
evaluation of the Si55x VCXO device either by itself  
(open-loop) or within a prototype PLL (closed-loop). The  
performance of the Si53x XO device can also be  
evaluated on this board (the Vc port is not used for XO  
devices).  
conveniently accessible through an SMA jack (J3) but  
can also be driven (and observed) through 100 mil-  
centered posts (JP4). For prototyping purposes, two  
0603 solder pads are located near the device V input  
C
(R3 and C3). A traditional PLL might use these as a  
single-time-constant low-pass filter (RC filter). The EVB  
is shipped with a 0 Ω resistor soldered at R3; C3 is left  
open. The voltage control input is not used for XO  
devices.  
Table 1. Jumper Control  
Part Type  
JP1  
JP2  
JP3  
JP4  
1.3. Output Clock  
Si530  
Si532  
Si534  
Si550  
Si552  
Si554  
Notes:  
N/A  
N/A  
N/A  
N/A  
OE  
OE  
N/A  
Freq Sel  
N/A  
Because the Si55x/Si53x devices can support an  
LVPECL buffer type (in addition to LVDS and CMOS),  
pulldown resistors (R1 and R2) are available for proper  
output biasing. For LVPECL buffers, biasing can be  
achieved through a variety of equivalent circuits; the  
Si5xx-EVB allows for 130 Ω pulldown resistors. After  
the output biasing, the high-speed outputs are dc-  
blocked for connection to differently biased inputs, such  
as standard test equipment or a phase detector EVB.  
Please review “1.4. Preparing the EVB” for non-LVPECL  
devices.  
Freq Sel1 Freq Sel2  
OE  
N/A  
N/A  
N/A  
N/A  
OE  
V
V
V
C
C
C
Freq Sel  
OE  
Freq Sel1 Freq Sel2  
1. With jumper(s) installed, signal(s) are driven low.  
2. With jumper(s) not installed, signal(s) are pulled high.  
1.1. Power Supply  
1.4. Preparing the EVB  
The Si55x/Si53x devices support operation from  
nominal voltages of 1.8, 2.5, and 3.3 V. Review the  
device data sheet and part number for allowed  
configurations of output buffer type and device power  
supply.  
By default, the evaluation board is set up to accept  
LVPECL configured devices. This configuration uses  
130 Ω pull-down resistors to bias the LVPECL output  
stage. If an LVDS, CMOS, or CML based device is to  
be installed, the output biasing resistors, R1 and R2,  
should be removed.  
2
Rev. 0.14