Si52147
Table 2. AC Electrical Specifications
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Crystal
Long-term Accuracy
Clock Input
L
Measured at V /2 differential
—
—
250
ppm
ACC
DD
CLKIN Duty Cycle
CLKIN Rise and Fall Times
T
Measured at V /2
47
—
—
53
%
DC
DD
T /T
Measured between 0.2 V and
0.5
4.0
V/ns
R
F
DD
0.8 V
DD
CLKIN Cycle to Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF at 0.7 V
T
Measured at VDD/2
Measured at VDD/2
XIN/CLKIN pin
—
—
2
—
—
—
—
—
—
250
350
ps
ps
V
CCJ
T
LTJ
V
VDD+0.3
0.8
IH
V
XIN/CLKIN pin
—
—
–35
V
IL
I
XIN/CLKIN pin, VIN = VDD
XIN/CLKIN pin, 0 < VIN <0.8
35
uA
uA
IH
I
—
IL
DIFF Duty Cycle
T
Measured at 0 V differential
Measured at 0 V differential
45
—
—
—
55
50
%
DC
Any DIFF Clock Skew from the T
Earliest Bank to the Latest
Bank
ps
SKEW(win
dow)
DIFF Cycle to Cycle Jitter
T
Measured at 0 V differential
—
0
35
40
50
ps
ps
CCJ
Output PCIe Gen1 REFCLK
Phase Jitter
RMS
108
Includes PLL BW 1.5–22 MHz,
ζ = 0.54, Td=10 ns,
GEN1
Ftrk=1.5 MHz with BER = 1E-12
Output PCIe Gen2 REFCLK
Phase Jitter
RMS
RMS
Includes PLL BW 8–16 MHz, Jitter
Peaking = 3 dB, ζ = 0.54, Td=12 ns,
Low Band, F < 1.5 MHz
0
0
0
2
2
3.0
3.1
1.0
ps
ps
ps
GEN2
GEN2
GEN3
Output PCIe Gen2 REFCLK
Phase Jitter
Includes PLL BW 8–16 MHz, Jitter
Peaking = 3 dB, ζ = 0.54, Td=12 ns,
High Band,1.5 MHz < F < Nyquist
Output Phase Jitter Impact— RMS
PCIe Gen3
Includes PLL BW 2–4 MHz,
CDR = 10 MHz
0.5
DIFF Long Term Accuracy
L
Measured at 0 V differential
—
1
—
—
100
8
ppm
V/ns
ACC
DIFF Rising/Falling Slew Rate
T /T
Measured differentially from
±150 mV
R
F
Voltage High
Voltage Low
V
—
—
—
—
1.15
—
V
V
HIGH
V
–0.3
300
LOW
Crossing Point Voltage at
0.7 V Swing
V
550
mV
OX
Enable/Disable and Setup
Clock Stabilization from
Power-up
T
—
—
—
1.8
—
ms
ns
STABLE
Stopclock Set-up Time
T
10.0
SS
Preliminary Rev. 0.1
5
SILICON [ SILICON ]
