Si1000/1/2/3/4/5
CP0EN
CP0OUT
CP0RIF
VDD
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0
Interrupt
CPT0MD
Analog Input Multiplexer
CP0
Rising-edge
CP0
Falling-edge
Px.x
CP0 +
Interrupt
Logic
Px.x
Px.x
CP0
+
-
SET
SET
CLR
D
Q
Q
D
Q
Q
CLR
Crossbar
(SYNCHRONIZER)
(ASYNCHRONOUS)
GND
CP0 -
CP0A
Reset
Decision
Tree
Px.x
Figure 1.13. Comparator 0 Functional Block Diagram
CP1EN
CP1OUT
CP1RIF
CP1FIF
VDD
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1
Interrupt
CPT0MD
Analog Input Multiplexer
CP1
Rising-edge
CP1
Falling-edge
Px.x
CP1 +
Interrupt
Logic
Px.x
Px.x
CP1
+
-
SET
SET
CLR
D
Q
Q
D
Q
Q
CLR
Crossbar
(SYNCHRONIZER)
(ASYNCHRONOUS)
GND
CP1 -
CP1A
Reset
Decision
Tree
Px.x
Figure 1.14. Comparator 1 Functional Block Diagram
26
Rev. 1.0