Si1000/1/2/3/4/5
SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2
Bit
7
6
XBARE
R/W
0
5
4
3
2
1
0
Name WEAKPUD
Type
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
SFR Page = 0x0; SFR Address = 0xE3
Bit
Name
Function
7
WEAKPUD Port I/O Weak Pullup Disable
0: Weak Pullups enabled (except for Port I/O pins configured for analog mode).
6
XBARE
Unused
Crossbar Enable
0: Crossbar disabled.
1: Crossbar enabled.
5:0
Read = 000000b; Write = Don’t Care.
Note: The Crossbar must be enabled (XBARE = 1) to use any Port pin as a digital output.
21.4. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMAT registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMAT registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(PnMAT & P0MASK) or if (P1 & P1MASK) does not equal (PnMAT & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode.
See Section “12. Interrupt Handler” on page 129 and Section “14. Power Management” on page 151 for
more details on interrupt and wake-up sources.
216
Rev. 1.0
SILICON [ SILICON ]
