欢迎访问ic37.com |
会员登录 免费注册
发布采购

SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
 浏览型号SI1002-C-GM的Datasheet PDF文件第73页浏览型号SI1002-C-GM的Datasheet PDF文件第74页浏览型号SI1002-C-GM的Datasheet PDF文件第75页浏览型号SI1002-C-GM的Datasheet PDF文件第76页浏览型号SI1002-C-GM的Datasheet PDF文件第78页浏览型号SI1002-C-GM的Datasheet PDF文件第79页浏览型号SI1002-C-GM的Datasheet PDF文件第80页浏览型号SI1002-C-GM的Datasheet PDF文件第81页  
Si1000/1/2/3/4/5  
5.2.2. Tracking Modes  
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to  
be accurate. The minimum tracking time is given in Table 4.9. The AD0TM bit in register ADC0CN controls  
the ADC0 track-and-hold mode. In its default state when Burst Mode is disabled, the ADC0 input is contin-  
uously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in  
low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR  
clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in  
low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of  
CNVSTR (see Figure 5.2). Tracking can also be disabled (shutdown) when the device is in low power  
standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are fre-  
quently changed, due to the settling time requirements described in “5.2.4. Settling Time Requirements” on  
page 79.  
A. ADC0 Timing for External Trigger Source  
CNVSTR  
(AD0CM[2:0]=100)  
1
2 3 4 5 6 7 8 9 10 11 12 13 14  
SAR Clocks  
AD0TM=1  
Low Power  
or Convert  
Low Power  
Mode  
Track  
Convert  
Convert  
AD0TM=0  
Track or Convert  
Track  
B. ADC0 Timing for Internal Trigger Source  
Write '1' to AD0BUSY,  
Timer 0, Timer 2,  
Timer 1, Timer 3 Overflow  
(AD0CM[2:0]=000, 001,010  
011, 101)  
1
1
2
3
4
4
5
5
6
6
7
7
8
8
9 10 11 12 13 14 15 16 17  
SAR  
Clocks  
Low Power  
or Convert  
Track  
Convert  
Low Power Mode  
AD0TM=1  
2
3
9 10 11 12 13 14  
SAR  
Clocks  
Track or  
Convert  
Convert  
Track  
AD0TM=0  
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0)  
Rev. 1.0  
77