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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The  
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is  
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by  
reading SPI0DAT.  
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire  
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when  
NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and  
is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in  
this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and  
a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0  
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will  
typically default to being slave devices while they are not acting as the system master device. In multi-  
master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.  
Figure 26.2 shows a connection diagram between two master devices in multiple-master mode.  
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this  
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices  
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 26.3  
shows a connection diagram between a master device in 3-wire master mode and a slave device.  
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an  
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value  
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be  
addressed using general-purpose I/O pins. Figure 26.4 shows a connection diagram for a master device in  
4-wire master mode and two slave devices.  
NSS  
MISO  
MOSI  
SCK  
GPIO  
MISO  
MOSI  
SCK  
Master  
Device 1  
Master  
Device 2  
GPIO  
NSS  
Figure 26.2. Multiple-Master Mode Connection Diagram  
Master  
Device  
Slave  
Device  
MISO  
MOSI  
SCK  
MISO  
MOSI  
SCK  
Figure 26.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram  
Rev. 1.0  
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