Si1000/1/2/3/4/5
Interrupt Enable enwut =1( Reg 06h)
WUT Period
GPIOX =00001
nIRQ
SPI Interrupt
Read
Chip State
Sleep
Ready
Sleep
Ready
Sleep
Ready
1.5 mA
Sleep
1.5 mA
1.5 mA
Current
Consumption
1 uA
1 uA
1 uA
Interrupt Enable enwut =0( Reg 06h)
WUT Period
GPIOX =00001
nIRQ
SPI Interrupt
Read
Chip State
Sleep
Current
Consumption
1 uA
Figure 23.23. WUT Interrupt and WUT Operation
23.8.7. Low Duty Cycle Mode
The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is
available. The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid
preamble or sync word is not detected the chip will return to sleep mode until the beginning of a new WUT
period. If a valid preamble and sync are detected the receiver on period will be extended for the low duty
cycle mode duration (TLDC) to receive all of the packet. The WUT period must be set in conjunction with
the low duty cycle mode duration. The R value (“Register 14h. Wake-up Timer Period 1”) is shared
Rev. 1.0
277
SILICON [ SILICON ]
