Si1000/1/2/3/4/5
Table 23.6. POR Parameters
Comment
Parameter
Symbol
VRR
Min
0.85
0.03
0.7
50
Typ
1.3
—
Max
1.75
300
1.3
470
—
Unit
V
Release Reset Voltage
Power-On V Slope
SVDD
VLD
tested V slope region
V/ms
V
DD
DD
Low V Limit
VLD<VRR is guaranteed
1
DD
Software Reset Pulse
Threshold Voltage
Reference Slope
TSWRST
VTSD
k
—
us
—
0.4
0.2
16
V
—
—
V/ms
ms
V
Glitch Reset Pulse
TP
Also occurs after SDN, and
initial power on
5
25
DD
The reset will initialize all registers to their default values. The reset signal is also available for output and
use by the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by
default on GPIO_1.
23.8.2. Output Clock
The 30 MHz crystal oscillator frequency is divided down internally and may be output on GPIO2. This fea-
ture is useful to lower BOM cost by using only one crystal in the system. The output clock on GPIO2 may
be routed to the XTAL2 input to provide a synchronized clock source between the MCU and the EZRadio-
PRO peripheral. The output clock frequency is selectable from one of 8 options, as shown below. Except
for the 32.768 kHz option, all other frequencies are derived by dividing the crystal oscillator frequency. The
32.768 kHz clock signal is derived from an internal RC oscillator or an external 32 kHz crystal. The default
setting for GPIO2 is to output the clock signal with a frequency of 1 MHz.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
0A R/W
Output Clock
clkt[1] clkt[0] enlfc mclk[2] mclk[1] mclk[0]
06h
mclk[2:0]
000
Modulation Source
30 MHz
001
15 MHz
010
10 MHz
011
4 MHz
100
3 MHz
101
2 MHz
110
1 MHz
111
32.768 kHz
Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz
clock can be automatically switched to become the output clock. This feature is called enable low fre-
quency clock and is enabled by the enlfc bit in “Register 0Ah. Microcontroller Output Clock." When enlfc =
1 and the chip is in SLEEP mode then the 32.768 kHz clock will be provided regardless of the setting of
mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin in all IDLE,
270
Rev. 1.0
SILICON [ SILICON ]
