Si1000/1/2/3/4/5
23.6.3. Packet Handler TX Mode
If the TX packet length is set the packet handler will send the number of bytes in the packet length field
before returning to IDLE mode and asserting the packet sent interrupt. To resume sending data from the
FIFO the microcontroller needs to command the chip to re-enter TX mode. Figure 23.13 provides an exam-
ple transaction where the packet length is set to three bytes.
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
This will be sent in the first transmission
}
}
}
This will be sent in the second transmission
This will be sent in the third transmission
Figure 23.13. Multiple Packets in TX Packet Handler
23.6.4. Packet Handler RX Mode
23.6.4.1. Packet Handler Disabled
When the packet handler is disabled certain fields in the received packet are still required. Proper modem
operation requires preamble and sync when the FIFO is being used, as shown in Figure 23.14. Bits after
sync will be treated as raw data with no qualification. This mode allows for the creation of a custom packet
handler when the automatic qualification parameters are not sufficient. Manchester encoding is supported
but data whitening, CRC, and header checks are not.
Preamble
SYNC
DATA
Figure 23.14. Required RX Packet Structure with Packet Handler Disabled
23.6.4.2. Packet Handler Enabled
When the packet handler is enabled, all the fields of the packet structure need to be configured. Register
contents are used to construct the header field and length information encoded into the transmitted packet
when transmitting. The receive FIFO can be configured to handle packets of fixed or variable length with or
without a header. If multiple packets are desired to be stored in the FIFO, then there are options available
for the different fields that will be stored into the FIFO. Figure 23.15 demonstrates the options and settings
available when multiple packets are enabled. Figure 23.16 demonstrates the operation of fixed packet
length and correct/incorrect packets.
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SILICON [ SILICON ]
