Si1000/1/2/3/4/5
Internal Register Definition 20.4. RTC0CN: SmaRTClock Control
Bit
7
6
5
4
3
2
1
0
RTC0EN MCLKEN OSCFAIL RTC0TR RTC0AEN
ALRM
RTC0SET RTC0CAP
Name
Type
Reset
R/W
0
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Varies
SmaRTClock Address = 0x04
Bit
Name
Function
7
RTC0EN SmaRTClock Enable.
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
6
MCLKEN Missing SmaRTClock Detector Enable.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock detector disabled.
1: Missing SmaRTClock detector enabled.
5
4
OSCFAIL SmaRTClock Oscillator Fail Event Flag.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be
cleared by software. The value of this bit is not defined when the SmaRTClock
oscillator is disabled.
RTC0TR SmaRTClock Timer Run Control.
Controls if the SmaRTClock timer is running or stopped (holds current value).
0: SmaRTClock timer is stopped.
1: SmaRTClock timer is running.
3
2
RTC0AEN SmaRTClock Alarm Enable.
Enables/disables the SmaRTClock alarm function. Also clears the ALRM flag.
0: SmaRTClock alarm disabled.
1: SmaRTClock alarm enabled.
ALRM
SmaRTClock Alarm Event Read:
Write:
Flag and Auto Reset
Enable
0: SmaRTClock alarm
event flag is de-asserted.
1: SmaRTClock alarm
event flag is asserted.
0: Disable Auto Reset.
1: Enable Auto Reset.
Reads return the state of the
alarm event flag.
Writes enable/disable the
Auto Reset function.
1
0
RTC0SET SmaRTClock Timer Set.
Writing 1 initiates a SmaRTClock timer set operation. This bit is cleared to 0 by hard-
ware to indicate that the timer set operation is complete.
RTC0CAP SmaRTClock Timer Capture.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by
hardware to indicate that the timer capture operation is complete.
Note: The ALRM flag will remain asserted for a maximum of one SmaRTClock cycle. See Section “Power
Management” on page 151 for information on how to capture a SmaRTClock Alarm event using a flag which is
not automatically cleared by hardware.
Rev. 1.0
203