Si1000/1/2/3/4/5
CIP-51 8051
Controller Core
Analog Peripherals
RF XCVR
(240-960 MHz,
+20 dBm)
Power On
Reset/PMU
6-bit
Wake
Reset
64k Byte ISP Flash
Program Memory
IREF0
IREF
PA
TX
External
VREF
Internal
VREF
256 Byte SRAM
4096 Byte XRAM
Debug /
C2CK/RST
AGC
VDD
VREF
Programming
Hardware
RXp
A
M
U
X
10-bit
RXn
Temp
Sensor
LNA
300ksps
ADC
C2D
Mixer
PGA
ADC
CRC
Engine
GND
VDD
GND
VREG
CP0, CP0A
CP1, CP1A
+
SYSCLK
-
+
-
Comparators
Digital Peripherals
Transceiver Control Interface
SFR
Bus
Digital
Modem
Precision
24.5 MHz
Oscillator
Delta
Sigma
Modulator
Low Power
20 MHz
Oscillator
Digital
Logic
UART
External
Oscillator
Circuit
P0.2/XTAL1
P0.3/XTAL2
XIN
XOUT
Timers 0,
1, 2, 3
OSC
Priority
Crossbar
Decoder
WDT
PCA/
XTAL3
XTAL4
SmaRTClock
Oscillator
SMBus
SPI 0
22
ANALOG &
DIGITAL I/O
System Clock
Configuration
Port I/O
Config
Figure 1.1. Si1000 Block Diagram
CIP-51 8051
Controller Core
Analog Peripherals
RF XCVR
Power On
Reset/PMU
(240-960 MHz,
+20 dBm)
6-bit
Wake
Reset
32k Byte ISP Flash
Program Memory
IREF0
IREF
PA
TX
External
VREF
Internal
VREF
256 Byte SRAM
4096 Byte XRAM
Debug /
C2CK/RST
AGC
LNA
VDD
VREF
Programming
Hardware
RXp
RXn
A
M
U
X
10-bit
Temp
Sensor
300ksps
ADC
C2D
Mixer
PGA
ADC
CRC
Engine
GND
VDD
GND
VREG
CP0, CP0A
CP1, CP1A
+
SYSCLK
-
+
-
Comparators
Digital Peripherals
Transceiver Control Interface
SFR
Bus
Digital
Modem
Precision
24.5 MHz
Oscillator
Delta
Sigma
Modulator
Low Power
20 MHz
Oscillator
Digital
Logic
UART
External
Oscillator
Circuit
P0.2/XTAL1
P0.3/XTAL2
XIN
XOUT
Timers 0,
1, 2, 3
OSC
Priority
Crossbar
Decoder
WDT
PCA/
XTAL3
XTAL4
SmaRTClock
Oscillator
SMBus
SPI 0
22
ANALOG &
DIGITAL I/O
System Clock
Configuration
Port I/O
Config
Figure 1.2. Si1001 Block Diagram
Rev. 1.0
17
SILICON [ SILICON ]
