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SI1003 参数 Datasheet PDF下载

SI1003图片预览
型号: SI1003
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable  
and re-enable) the SMBus in the event of an SCL low timeout.  
24.3.5. SCL High (SMBus Free) Timeout  
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus  
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and  
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the  
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated  
following this timeout. Note that a clock source is required for free timeout detection, even in a slave-only  
implementation.  
24.4. Using the SMBus  
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-  
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides  
the following application-independent features:  
Byte-wise serial data transfers  
Clock signal generation on SCL (Master Mode only) and SDA data synchronization  
Timeout/bus error recognition, as defined by the SMB0CF configuration register  
START/STOP timing, detection, and generation  
Bus arbitration  
Interrupt generation  
Status information  
Optional hardware recognition of slave address and automatic acknowledgement of address/data  
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware  
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard-  
ware is acting as a data transmitter or receiver. When a transmitter (i.e. sending address/data, receiving an  
ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;  
when receiving data (i.e. receiving address/data, sending an ACK), this interrupt is generated before the  
ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement is enabled,  
these interrupts are always generated after the ACK cycle. See Section 24.5 for more details on transmis-  
sion sequences.  
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or  
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control  
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 24.4.2;  
Table 24.5 provides a quick SMB0CN decoding reference.  
24.4.1. SMBus Configuration Register  
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,  
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is  
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the  
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,  
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit  
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of  
the current transfer).  
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Rev. 1.0