Si1000/1/2/3/4/5
SFR Definition 22.3. SPI1CKR: SPI Clock Rate
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SCR1[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x85
Bit
Name
Function
7:0
SCR1
SPI Clock Rate.
These bits determine the frequency of the SCK output when the SPI module is
configured for master mode operation. The SCK clock frequency is a divided
version of the system clock, and is given in the following equation, where SYSCLK
is the system clock frequency and SPI1CKR is the 8-bit value held in the SPI1CKR
register.
SYSCLK
fSCK = ----------------------------------------------------------
2 SPI1CKR[7:0] + 1
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI1CKR = 0x04,
2000000
fSCK = -------------------------
2 4 + 1
fSCK = 200kHz
236
Rev. 1.0
SILICON [ SILICON ]
