Si1000/1/2/3/4/5
SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0
Bit
7
CP1AE
R/W
0
6
CP1E
R/W
0
5
CP0AE
R/W
0
4
CP0E
R/W
0
3
SYSCKE
R/W
2
SMB0E
R/W
0
1
SPI0E
R/W
0
0
URT0E
R/W
0
Name
Type
Reset
0
SFR Page = 0x0; SFR Address = 0xE1
Bit
Name
Function
7
CP1AE Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 output unavailable at Port pin.
1: Asynchronous CP1 output routed to Port pin.
6
5
4
3
2
1
CP1E
Comparator1 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
CP0AE Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 output unavailable at Port pin.
1: Asynchronous CP0 output routed to Port pin.
CP0E
Comparator0 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
SYSCKE SYSCLK Output Enable.
0: SYSCLK output unavailable at Port pin.
1: SYSCLK output routed to Port pin.
SMB0E SMBus I/O Enable.
0: SMBus I/O unavailable at Port pin.
1: SDA and SCL routed to Port pins.
SPI0E
SPI0 I/O Enable
0: SPI0 I/O unavailable at Port pin.
1: SCK, MISO, and MOSI (for SPI0) routed to Port pins.
NSS (for SPI0) routed to Port pin only if SPI0 is configured to 4-wire mode.
0
URT0E Comparator1 Asynchronous Output Enable.
0: UART I/O unavailable at Port pin.
1: TX0 and RX0 routed to Port pins P0.4 and P0.5.
Note: SPI0 can be assigned either 3 or 4 Port I/O pins.
214
Rev. 1.0
SILICON [ SILICON ]
