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SI1003 参数 Datasheet PDF下载

SI1003图片预览
型号: SI1003
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
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文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
14.2. Idle Mode  
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon  
as the instruction that sets the bit completes execution. All internal registers and memory maintain their  
original data. All analog and digital peripherals can remain active during Idle mode.  
Note: To ensure the MCU enters a low power state upon entry into Idle Mode, the one-shot circuit should be  
enabled by clearing the BYPASS bit (FLSCL.6) to logic 0. See the note in SFR Definition 13.3. FLSCL:  
Flash Scale for more information on how to properly clear the BYPASS bit.  
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an  
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume  
operation. The pending interrupt will be serviced and the next instruction to be executed after the return  
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.  
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence  
and begins program execution at address 0x0000.  
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-  
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event  
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by  
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-  
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-  
nitely, waiting for an external stimulus to wake up the system. Refer to Section “18.6. PCA Watchdog Timer  
Reset” on page 180 for more information on the use and configuration of the WDT.  
14.3. Stop Mode  
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-  
tion that sets the bit completes execution. In Stop mode the precision internal oscillator and CPU are  
stopped; the state of the low power oscillator and the external oscillator circuit is not affected. Each analog  
peripheral (including the external oscillator circuit) may be shut down individually prior to entering Stop  
Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs  
the normal reset sequence and begins program execution at address 0x0000.  
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.  
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the  
MCD timeout of 100 µs.  
Stop Mode is a legacy 8051 power mode; it will not result in optimal power savings. Sleep or Suspend  
mode will provide more power savings if the MCU needs to be inactive for a long period of time.  
On Si1000/1/2/3/4/5 devices, the Precision Oscillator Bias is not automatically disabled and should be dis-  
abled by software to achieve the lowest possible Stop mode current.  
To ensure the MCU enters a low power state upon entry into Stop Mode, the one-shot circuit should be  
enabled by clearing the BYPASS bit (FLSCL.6) to logic 0. See the note in SFR Definition 13.3. FLSCL: Flash  
Scale for more information on how to properly clear the BYPASS bit.  
Rev. 1.0  
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