Si1000/1/2/3/4/5
CIP-51 8051
Controller Core
Analog Peripherals
RF XCVR
(240-960 MHz)
Power On
Reset/PMU
6-bit
Wake
Reset
64k Byte ISP Flash
Program Memory
IREF0
IREF
PA
TX
External
VREF
Internal
VREF
256 Byte SRAM
4096 Byte XRAM
Debug /
C2CK/RST
AGC
VDD
VREF
Programming
Hardware
RXp
A
M
U
X
10-bit
RXn
Temp
Sensor
LNA
300ksps
ADC
C2D
Mixer
PGA
ADC
CRC
Engine
GND
Power Net
VDD/DC+
GND/DC-
VREG
CP0, CP0A
CP1, CP1A
+
Analog
Power
Digital
Power
SYSCLK
-
+
-
Comparators
Digital Peripherals
Transceiver Control Interface
SFR
Bus
Digital
Modem
Precision
24.5 MHz
Oscillator
Delta
Sigma
Modulator
DC/DC
Converter
VBAT
GND
Low Power
20 MHz
Oscillator
Digital
Logic
UART
External
Oscillator
Circuit
XTAL1
XIN
XOUT
Timers 0,
1, 2, 3
OSC
XTAL2
Priority
Crossbar
Decoder
WDT
PCA/
XTAL3
XTAL4
SmaRTClock
Oscillator
SMBus
SPI 0
19
ANALOG &
DIGITAL I/O
System Clock
Configuration
Port I/O
Config
Figure 1.5. Si1004 Block Diagram
CIP-51 8051
Controller Core
Analog Peripherals
RF XCVR
(240-960 MHz)
Power On
Reset/PMU
6-bit
Wake
Reset
32k Byte ISP Flash
Program Memory
IREF0
IREF
PA
TX
External
VREF
Internal
VREF
256 Byte SRAM
4096 Byte XRAM
Debug /
C2CK/RST
AGC
LNA
VDD
VREF
Programming
Hardware
RXp
RXn
A
M
U
X
10-bit
Temp
Sensor
300ksps
ADC
C2D
Mixer
PGA
ADC
CRC
Engine
GND
Power Net
VDD/DC+
GND/DC-
VREG
CP0, CP0A
CP1, CP1A
+
Analog
Power
Digital
Power
SYSCLK
-
+
-
Comparators
Digital Peripherals
Transceiver Control Interface
SFR
Bus
Digital
Modem
Precision
24.5 MHz
Oscillator
Delta
Sigma
Modulator
DC/DC
Converter
VBAT
GND
Low Power
20 MHz
Oscillator
Digital
Logic
UART
External
Oscillator
Circuit
XTAL1
XTAL2
XIN
XOUT
Timers 0,
1, 2, 3
OSC
Priority
Crossbar
Decoder
WDT
PCA/
XTAL3
XTAL4
SmaRTClock
Oscillator
SMBus
SPI 0
19
ANALOG &
DIGITAL I/O
System Clock
Configuration
Port I/O
Config
Figure 1.6. Si1005 Block Diagram
Rev. 1.0
19