Si1000/1/2/3/4/5
14.1. Normal Mode
The MCU is fully functional in Normal Mode. Figure 14.1 shows the on-chip power distribution to various
peripherals. There are three supply voltages powering various sections of the chip: VBAT, VDD/DC+, and
the 1.8 V internal core supply. VREG0, PMU0 and the SmaRTClock are always powered directly from the
VBAT pin. All analog peripherals are directly powered from the VDD/DC+ pin, which is an output in one-cell
mode and an input in two-cell mode. All digital peripherals and the CIP-51 core are powered from the 1.8 V
internal core supply. The RAM is also powered from the core supply in Normal mode.
One-cell: 0.9 to 1.8 V
Two-cell: 1.8 to 3.6 V
VBAT
VDD/DC+
One-cell or Two-cell: 1.8 to 3.6 V
Note: VDD/DC+ must be > VBAT
1.9 V
typical
GPIO
DC0
Analog Peripherals
One-Cell Active/
Idle/Stop/Suspend
One-Cell Sleep
VREF
IREF0
A
10-bit
300 ksps
ADC
M
U
X
+
-
+
-
VREG0
TEMP
SENSOR
VOLTAGE
COMPARATORS
Active/Idle/
Stop/Suspend
Sleep
Digital Peripherals
1.8 V
UART
Flash
PMU0
SmaRTClock
CIP-51
Core
SPI
RAM
Timers
SMBus
Figure 14.1. Si1000/1/2/3/4/5 Power Distribution
152
Rev. 1.0
SILICON [ SILICON ]
