Si1000/1/2/3/4/5
SFR Definition 22.2. SPI1CN: SPI Control
Bit
7
6
5
4
3
2
1
0
SPI1EN
R/W
0
Name SPIF1 WCOL1 MODF1
NSS1MD1 NSS1MD0
TXBMT1
Type
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R
1
Reset
SFR Page = 0x0; SFR Address = 0xB0; Bit-Addressable
Bit
Name
Function
7
SPIF1
SPI1 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are
enabled, setting this bit causes the CPU to vector to the SPI1 interrupt service
routine. This bit is not automatically cleared by hardware. It must be cleared by
software.
6
5
4
WCOL1
MODF1
Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI1 interrupt) to indicate a
write to the SPI1 data register was attempted while a data transfer was in progress.
It must be cleared by software.
Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI1 interrupt) when a mas-
ter mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01).
This bit is not automatically cleared by hardware. It must be cleared by software.
Reserved.
Read = varies; Write = must write zero.
3:2 NSS1MD[1:0] Slave Select Mode.
Must be set to 00b. SPI1 can only be used in 3-wire master mode.
Transmit Buffer Empty.
1
TXBMT1
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0
SPI1EN
SPI1 Enable.
0: SPI1 disabled.
1: SPI1 enabled.
Rev. 1.0
235