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SI1005-C-GM 参数 Datasheet PDF下载

SI1005-C-GM图片预览
型号: SI1005-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
19.4. Special Function Registers for Selecting and Configuring the System Clock  
The clocking sources on Si1000/1/2/3/4/5 devices are enabled and configured using the OSCICN,  
OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time  
Clock)” on page 190 for SmaRTClock register descriptions. The system clock source for the MCU can be  
selected using the CLKSEL register. To minimize active mode current, the oneshot timer which sets Flash  
read time should by bypassed when the system clock is greater than 10 MHz. See the FLSCL register  
description for details.  
The clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching  
between two clock divide values, the transition may take up to 128 cycles of the undivided clock source.  
The CLKRDY flag can be polled to determine when the new clock divide value has been applied. The clock  
divider must be set to "divide by 1" when entering Suspend or Sleep Mode.  
The system clock source may also be switched on-the-fly. The switchover takes effect after one clock  
period of the slower oscillator.  
SFR Definition 19.1. CLKSEL: Clock Select  
Bit  
7
6
5
4
3
2
1
0
CLKRDY  
CLKDIV[2:0]  
CLKSEL[2:0]  
Name  
Type  
Reset  
R
0
R/W  
0
R/W  
1
R/W  
1
R/W  
0
R/W  
1
R/W  
0
R/W  
0
SFR Page = All Pages; SFR Address = 0xA9  
Bit  
Name  
Function  
7
CLKRDY  
System Clock Divider Clock Ready Flag.  
0: The selected clock divide setting has not been applied to the system clock.  
1: The selected clock divide setting has been applied to the system clock.  
6:4  
CLKDIV[2:0] System Clock Divider Bits.  
Selects the clock division to be applied to the undivided system clock source.  
000: System clock is divided by 1.  
001: System clock is divided by 2.  
010: System clock is divided by 4.  
011: System clock is divided by 8.  
100: System clock is divided by 16.  
101: System clock is divided by 32.  
110: System clock is divided by 64.  
111: System clock is divided by 128.  
Read = 0b. Must Write 0b.  
3
Unused  
2:0  
CLKSEL[2:0] System Clock Select.  
Selects the oscillator to be used as the undivided system clock source.  
000: Precision Internal Oscillator.  
001: External Oscillator.  
010: Reserved.  
011: SmaRTClock Oscillator.  
1xx: Low Power Oscillator.  
Rev. 1.0  
187