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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
20. Port Input/Output  
Digital and analog resources are available through 40 (C8051F500/1/4/5), 33 (C8051F508/9-F510/1) or 25  
(C8051F502/3/6/7) I/O pins. Port pins P0.0-P4.7 on the C8051F500/1/4/5, port pins P0.0-P4.0 on  
theC8051F508/9-F510/1, and port pins P0.0-P3.0 on the C8051F502/3/6/7 can be defined as general-pur-  
pose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an analog function as  
shown in Figure 20.3. Port pin P4.0 on the C8051F508/9-F510/1 can be used as GPIO and is shared with  
the C2 Interface Data signal (C2D). Similarly, port pin P3.0 is shared with C2D on the C8051F502/3/6/7.  
The designer has complete control over which functions are assigned, limited only by the number of phys-  
ical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar  
Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regard-  
less of the Crossbar settings.  
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder  
(Figure 20.3 and Figure 20.4). The registers XBR0, XBR1, XBR2 are defined in SFR Definition 20.1 and  
SFR Definition 20.2 and are used to select internal digital functions.  
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured  
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete  
Electrical Specifications for Port I/O are given in Table 5.3 on page 45.  
XBR0, XBR1,  
XBR2, PnSKIP  
PnMDOUT,  
PnDMIN Registers  
External  
Pins  
Priority  
Decoder  
2
2
4
2
P0.0  
Highest  
Priority  
P0  
I/O  
Cells  
UART0  
CAN0  
8
8
8
8
8
Highest  
Priority  
P0.7  
Digital  
Crossbar  
SPI0  
P1.0  
P1.7  
P1  
I/O  
Cells  
SMBus0  
2
2
CP0  
P2.0  
P2.7  
P2  
I/O  
Cells  
CP1  
/SYSCLK  
7
4
PCA0  
P3.0  
P3.7  
P3  
I/O  
Cells  
T0, T1,  
/INT0,  
/INT1  
Lowest  
Priority  
2
LIN0  
P4.0  
P4.7  
P4  
I/O  
Cells  
Lowest  
Priority  
8 x 5  
P0  
P1  
P2  
P3  
P4  
Port  
Latches  
(Px.0-Px.7)  
8 x 5  
PnMASK  
PnMATCH  
Registers  
Figure 20.1. Port I/O Functional Block Diagram  
Rev. 1.1  
177