C8051F50x-F51x
SFR Definition 15.4. CCH0CN: Cache Control
Bit
7
6
5
4
3
2
1
0
Name Reserved Reserved CHPFEN Reserved Reserved Reserved Reserved CHBLKW
Type
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
SFR Address = 0xE3; SFR Page = 0x0F
Bit Name
7:6 Reserved Must Write 00b
CHPFEN Cache Prefect Enable Bit.
Function
5
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
4:1 Reserved Must Write 0000b.
0
CHBLKW Block Write Enable Bit.
This bit allows block writes to Flash memory from firmware.
0: Each byte of a software Flash write is written individually.
1: Flash bytes are written in groups of two.
SFR Definition 15.5. ONESHOT: Flash Oneshot Period
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PERIOD[3:0]
R/W R/W
R
0
R
0
R
0
R
0
R/W
1
R/W
1
1
1
SFR Address = 0xBE; SFR Page = 0x0F
Bit
Name
Function
7:4
Unused
Read = 0000b. Write = don’t care.
3:0 PERIOD[3:0] Oneshot Period Control Bits.
These bits limit the internal Flash read strobe width as follows. When the Flash read
strobe is de-asserted, the Flash memory enters a low-power state for the remainder
of the system clock cycle. These bits have no effect when the system clocks is
greater than 12.5 MHz and FLRT = 0.
FLASHRDMAX = 5ns + PERIOD 5ns
Rev. 1.1
137
SILICON [ SILICON ]
