C8051F50x-F51x
Table 14.1. Interrupt Summary
Interrupt Source
Interrupt Priority
Pending Flag
Enable
Flag
Priority
Control
Vector
Order
Reset
0x0000
0x0003
Top
0
None
N/A N/A
Always
Enabled
EX0 (IE.0) PX0 (IP.0)
Always
Highest
External Interrupt 0
(INT0)
IE0 (TCON.1)
Y
Y
Timer 0 Overflow
External Interrupt 1
(INT1)
0x000B
0x0013
1
2
TF0 (TCON.5)
IE1 (TCON.3)
Y
Y
Y
Y
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow
UART0
0x001B
0x0023
3
4
TF1 (TCON.7)
RI0 (SCON0.0)
Y
Y
Y
N
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
TI0 (SCON0.1)
Timer 2 Overflow
SPI0
0x002B
0x0033
5
6
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SI (SMB0CN.0)
Y
Y
N
N
ET2 (IE.5) PT2 (IP.5)
ESPI0
(IE.6)
PSPI0
(IP.6)
SMB0
0x003B
0x0043
0x004B
0x0053
7
8
Y
Y
Y
Y
N
N
N
N
ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
ADC0 Window Com-
pare
ADC0 Conversion
Complete
Programmable
Counter Array
AD0WINT
(ADC0CN.3)
AD0INT (ADC0CN.5)
EWADC0 PWADC0
(EIE1.1)
EADC0
(EIE1.2)
EPCA0
(EIE1.3)
(EIP1.1)
PADC0
(EIP1.2)
PPCA0
(EIP1.3)
9
10
CF (PCA0CN.7)
CCFn (PCA0CN.n)
COVF (PCA0PWM.6)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
LIN0INT (LINST.3)
Comparator0
Comparator1
Timer 3 Overflow
LIN0
0x005B
0x0063
0x006B
0x0073
0x007B
0x0083
0x008B
11
12
13
14
15
16
17
N
N
N
N
N
N
ECP0
(EIE1.4)
ECP1
PCP0
(EIP1.4)
PCP1
(EIE1.5)
(EIP1.5)
N
ET3
PT3
(EIE1.6)
(EIP1.6)
N*
ELIN0
(EIE1.7)
PLIN0
(EIP1.7)
PREG0
(EIP2.0)
PCAN0
(EIP2.1)
PMAT
Voltage Regulator
Dropout
N/A
N/A N/A EREG0
(EIE2.0)
N
CAN0
CAN0INT
(CAN0CN.7)
Y
ECAN0
(EIE2.1)
EMAT
Port Match
None
N/A N/A
(EIE2.2)
(EIP2.2)
Note: The LIN0INT bit is cleared by setting RSTINT (LINCTRL.3)
Rev. 1.1
119
SILICON [ SILICON ]
