C8051F50x-F51x
Table 13.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
IT01CF
Address
0xE4
0xD3
0xC9
0xD2
0xA1
0xA2
0x9E
0x9F
0x80
0xF2
0xF1
0xF1
0xA4
0xD4
0x90
0xF4
0xF3
0xF2
0xA5
0xD5
0xA0
0xB2
0xB1
0xF3
0xA6
0xD6
0xB0
0xAF
0xAE
0xF4
0xAE
0xD7
0xB5
0xAF
0xD8
0xFC
Description
Page
128
208
208
209
168
169
169
173
191
187
187
192
192
193
193
188
188
194
194
195
195
189
189
196
196
197
197
190
190
198
198
199
199
200
300
305
INT0/INT1 Configuration
LIN0 Address
LIN0ADR
LIN0CF
LIN0DAT
OSCICN
OSCICRS
OSCIFIN
OSCXCN
P0
LIN0 Configuration
LIN0 Data
Internal Oscillator Control
Internal Oscillator Coarse Control
Internal Oscillator Fine Calibration
External Oscillator Control
Port 0 Latch
P0MASK
P0MAT
Port 0 Mask Configuration
Port 0 Match Configuration
Port 0 Input Mode Configuration
Port 0 Output Mode Configuration
Port 0 Skip
P0MDIN
P0MDOUT
P0SKIP
P1
Port 1 Latch
P1MASK
P1MAT
Port 1 Mask Configuration
Port 1 Match Configuration
Port 1 Input Mode Configuration
Port 1 Output Mode Configuration
Port 1 Skip
P1MDIN
P1MDOUT
P1SKIP
P2
Port 2 Latch
P2MASK
P2MAT
Port 2 Mask Configuration
Port 2 Match Configuration
Port 2 Input Mode Configuration
Port 2 Output Mode Configuration
Port 2 Skip
P2MDIN
P2MDOUT
P2SKIP
P3
Port 3 Latch
P3MASK
P3MAT
Port 3 Mask Configuration
Port 3 Match Configuration
Port 3 Input Mode Configuration
Port 3 Output Mode Configuration
Port 3 Skip
P3MDIN
P3MDOUT
P3SKIP
P4
Port 4 Latch
P4MDOUT
PCA0CN
PCA0CPH0
Port 4 Output Mode Configuration
PCA Control
PCA Capture 0 High
114
Rev. 1.1
SILICON [ SILICON ]
