C8051F96x
Ultra-Low-Power, High-Efficiency, Battery-Powered Metering MCU
Ultra-Low Power @ 3.6 V
High-Speed Enhanced 8051 µC Core
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110 µA/MHz, Low-Power Active, DC-DC enabled
110 nA sleep current with data retention; POR monitor enabled
400 nA sleep current with smaRTClock (internal LFO)
700 nA sleep current with smaRTClock (external XTAL)
2 µs wake-up from any sleep mode
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Pipe-lined instruction architecture executes 70% of instructions
in 1 or 2 system clocks
Memory
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Up to 128 kB Flash; In-system programmable; Full read/write/
erase functionality over the entire supply range
Up to 8 kB data retention RAM
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12-Bit; 16 ch. Analog to Digital Converter
Digital Peripherals
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Up to 75 ksps, 12-bit mode or 300 ksps 10-bit mode
Up to 57 port I/O; All 5 V tolerant with programmable drive
strength
Hardware enhanced UART, 2 SPI and I2C serial ports available
concurrently
External pin or internal VREF (no external capacitor required)
On-chip PGA allows measuring voltages up to twice the
reference voltage
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Autonomous burst mode with 16-bit automatic averaging
accumulator
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Four general-purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with six capture/com-
pare/PWM modules and watchdog timer
Integrated temperature sensor
Two Low Current Comparators
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Clock Sources
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Programmable hysteresis and response time
Precision internal oscillators: 24.5 MHz with ±2% accuracy sup-
ports UART operation; spread-spectrum mode for reduced EMI
Low power internal oscillator: 20 MHz
Configurable as interrupt or reset source
Internal 6-Bit Current Reference
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Up to ±500 µA; source and sink capability
External oscillator: Crystal, RC, C, CMOS clock
Enhanced resolution via PWM interpolation
SmaRTClock oscillator: 32.768 kHz crystal or 16.4 kHz internal
LFO with three independent alarms
Integrated LCD Controller
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Supports up to 128 segments (32x4)
On-Chip Debug
Integrated charge pump for contrast control
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On-chip debug circuitry facilitates full speed, non-intrusive in-
system debug (no emulator required)
Metering-Specific Peripherals
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Provides four breakpoints, single stepping
DC-DC buck converter allows dynamic voltage scaling for
maximum efficiency (250 mW output)
Package Options
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76-pin DQFN (6x6 mm), RoHS compliant
40-pin QFN (6x6 mm), RoHS compliant
80-pin QFP (12x12 mm), RoHS compliant
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Sleep-mode pulse accumulator with programmable switch
de-bounce and pull-up control interfaces directly to metering
sensor
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Data Packet Processing Engine (DPPE) includes hardware
AES, DMA, CRC, and encoding blocks for acceleration of wire-
less protocols
Development Kit: C8051F960DK
Supply Voltage: 1.8 to 3.8 V
Manchester and Three-out-of-Six encoder hardware for power-
efficient implementation of the wireless M-bus specification
Temperature Range: –40 to +85 °C
Port I/O Configuration
P0.0/VREF
CIP-51 8051
Power On
Controller Core
Reset/PMU
Wake
Reset
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
Digital Peripherals
UART
128k Byte ISP Flash
Program Memory
Port 0
Drivers
Timers
0, 1, 2, 3
256 Byte SRAM
8092 Byte XRAM
Debug /
Programming
Hardware
C2CK/RST
P0.6/CNVSTR
P0.7
Priority
Crossbar
Decoder
PCA/WDT
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
SMBus
SPI 0
C2D
VBAT
VDD
DMA
Analog
Power
VBAT
VDC
CRC
Engine
Port 1
Drivers
SPI 1
(DMA Enabled)
Digital
Power
VREG
P1.5/INT5
P1.6/INT6
P1.7
AES
Crossbar Control
Engine
Encoder
LCD (up to 4x32)
EMIF
SFR
Bus
P2.0/SCK1
P2.1/MISO1
P2.2/MOSI1
P2.3/NSS1
P2.4
VBATDC
IND
DC/DC Buck
Converter
SYSCLK
Precision
24.5 MHz
Oscillator
Port 2
Drivers
GNDDC
Pulse Counter
P2.5
P2.6
P2.7
Low Power
20 MHz
Oscillator
Analog Peripherals
LCD Charge
Pump
CAP
32
16
External
VREF
P3-6
Drivers
Internal
VREF
P3.0...P6.7
P7.0/C2D
External
Oscillator
Circuit
XTAL1
XTAL2
VDD
VREF
P7
Driver
A
M
U
X
12-bit
Temp
Sensor
75ksps
ADC
Enhanced
smaRTClock
Oscillator
XTAL3
XTAL4
GND
GND
CP0, CP0A
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System Clock
Configuration
CP1, CP1A
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Comparators
Low-Voltage/Low-Power
Copyright © 2011 by Silicon Laboratories
11.03.11
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