C8051F336/7/8/9
13.Memory Organization
Figure 13.1. C8051F336/7/8/9 Memory Map............................................................ 81
Figure 13.2. Flash Program Memory Map................................................................ 82
14.Special Function Registers
15.Interrupts
16.Flash Memory
Figure 16.1. Flash Program Memory Map.............................................................. 100
17.Power Management Modes
18.Reset Sources
Figure 18.1. Reset Sources.................................................................................... 110
Figure 18.2. Power-On and VDD Monitor Reset Timing ........................................ 111
19.Oscillators and Clock Selection
Figure 19.1. Oscillator Options............................................................................... 116
Figure 19.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram . 124
20.Port Input/Output
Figure 20.1. Port I/O Functional Block Diagram..................................................... 127
Figure 20.2. Port I/O Cell Block Diagram ............................................................... 128
Figure 20.3. Crossbar Priority Decoder with No Pins Skipped............................... 131
Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 132
21.SMBus
Figure 21.1. SMBus Block Diagram ....................................................................... 145
Figure 21.2. Typical SMBus Configuration............................................................. 146
Figure 21.3. SMBus Transaction............................................................................ 147
Figure 21.4. Typical SMBus SCL Generation......................................................... 150
Figure 21.5. Typical Master Write Sequence ......................................................... 158
Figure 21.6. Typical Master Read Sequence ......................................................... 159
Figure 21.7. Typical Slave Write Sequence ........................................................... 160
Figure 21.8. Typical Slave Read Sequence ........................................................... 161
22.UART0
Figure 22.1. UART0 Block Diagram ....................................................................... 166
Figure 22.2. UART0 Baud Rate Logic.................................................................... 167
Figure 22.3. UART Interconnect Diagram .............................................................. 168
Figure 22.4. 8-Bit UART Timing Diagram............................................................... 168
Figure 22.5. 9-Bit UART Timing Diagram............................................................... 169
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram .......................... 170
23.Enhanced Serial Peripheral Interface (SPI0)
Figure 23.1. SPI Block Diagram ............................................................................. 174
Figure 23.2. Multiple-Master Mode Connection Diagram....................................... 177
Figure 23.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
177
Figure 23.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
177
Figure 23.5. Master Mode Data/Clock Timing........................................................ 179
Figure 23.6. Slave Mode Data/Clock Timing (CKPHA = 0).................................... 180
Figure 23.7. Slave Mode Data/Clock Timing (CKPHA = 1).................................... 180
Rev. 0.2
9
SILICON [ SILICON ]
