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C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
24.3.2. 8-bit Timers with Auto-Reload  
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-  
ate in auto-reload mode as shown in Figure 24.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH  
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is  
always running when configured for 8-bit Mode.  
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock  
source divided by 8, or the internal Low-frequency Oscillator. The Timer 3 Clock Select bits (T3MH and  
T3ML in CKCON) select either SYSCLK or the clock defined by the Timer 3 External Clock Select bits  
(T3XCLK[1:0] in TMR3CN), as follows:  
T3MH  
T3XCLK[1:0]  
TMR3H Clock  
Source  
T3ML  
T3XCLK[1:0]  
TMR3L Clock  
Source  
0
0
0
0
1
00  
01  
10  
11  
X
SYSCLK / 12  
External Clock / 8  
Reserved  
Internal LFO  
SYSCLK  
0
0
0
0
1
00  
01  
10  
11  
X
SYSCLK / 12  
External Clock / 8  
Reserved  
Internal LFO  
SYSCLK  
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows  
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-  
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each  
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and  
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not  
cleared by hardware and must be manually cleared by software.  
CKCON  
T T T T T T S S  
3 3 2 2 1 0 C C  
T3XCLK[1:0]  
M M M MM M A A  
Reload  
TMR3RLH  
H L H L  
1 0  
SYSCLK / 12  
External Clock / 8  
Internal LFO / 8  
00  
0
1
01  
11  
TCLK  
TF3H  
TF3L  
TF3LEN  
TF3CEN  
T3SPLIT  
TR3  
TMR3H  
Interrupt  
TR3  
Reload  
T3XCLK1  
T3XCLK0  
TMR3RLL  
SYSCLK  
1
0
TCLK  
TMR3L  
To ADC  
Figure 24.8. Timer 3 8-Bit Mode Block Diagram  
204  
Rev. 0.2