欢迎访问ic37.com |
会员登录 免费注册
发布采购

C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
 浏览型号C8051F339的Datasheet PDF文件第170页浏览型号C8051F339的Datasheet PDF文件第171页浏览型号C8051F339的Datasheet PDF文件第172页浏览型号C8051F339的Datasheet PDF文件第173页浏览型号C8051F339的Datasheet PDF文件第175页浏览型号C8051F339的Datasheet PDF文件第176页浏览型号C8051F339的Datasheet PDF文件第177页浏览型号C8051F339的Datasheet PDF文件第178页  
C8051F336/7/8/9  
23. Enhanced Serial Peripheral Interface (SPI0)  
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous  
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-  
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input  
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding  
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can  
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-  
eral purpose port I/O pins can be used to select multiple slave devices in master mode.  
SFR Bus  
SPI0CKR  
SPI0CFG  
SPI0CN  
Clock Divide  
Logic  
SYSCLK  
SPI CONTROL LOGIC  
SPI IRQ  
Data Path  
Control  
Pin Interface  
Control  
MOSI  
Tx Data  
C
R
O
S
S
B
A
R
SPI0DAT  
SCK  
MISO  
NSS  
Transmit Data Buffer  
Pin  
Control  
Logic  
Port I/O  
Shift Register  
Rx Data  
7 6 5 4 3 2 1 0  
Receive Data Buffer  
Read  
SPI0DAT  
Write  
SPI0DAT  
SFR Bus  
Figure 23.1. SPI Block Diagram  
174  
Rev. 0.2