欢迎访问ic37.com |
会员登录 免费注册
发布采购

C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
 浏览型号C8051F339的Datasheet PDF文件第164页浏览型号C8051F339的Datasheet PDF文件第165页浏览型号C8051F339的Datasheet PDF文件第166页浏览型号C8051F339的Datasheet PDF文件第167页浏览型号C8051F339的Datasheet PDF文件第169页浏览型号C8051F339的Datasheet PDF文件第170页浏览型号C8051F339的Datasheet PDF文件第171页浏览型号C8051F339的Datasheet PDF文件第172页  
C8051F336/7/8/9  
22.2. Operational Modes  
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is  
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 22.3.  
TX  
RS-232  
RS-232  
LEVEL  
C8051Fxxx  
RX  
XLTR  
OR  
TX  
RX  
TX  
RX  
MCU  
C8051Fxxx  
Figure 22.3. UART Interconnect Diagram  
22.2.1. 8-Bit UART  
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop  
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data  
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).  
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-  
rupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data recep-  
tion can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is  
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:  
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data over-  
run, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits  
are lost.  
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the  
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not  
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.  
MARK  
START  
BIT  
STOP  
BIT  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
SPACE  
BIT TIMES  
BIT SAMPLING  
Figure 22.4. 8-Bit UART Timing Diagram  
168  
Rev. 0.2