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C8051F336 参数 Datasheet PDF下载

C8051F336图片预览
型号: C8051F336
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
SFR Definition 22.1. SCON0: Serial Port 0 Control  
Bit  
7
6
5
MCE0  
R/W  
0
4
REN0  
R/W  
0
3
TB80  
R/W  
0
2
RB80  
R/W  
0
1
TI0  
R/W  
0
0
RI0  
R/W  
0
Name S0MODE  
Type  
R/W  
0
R
1
Reset  
SFR Address = 0x98; Bit-Addressable  
Bit  
Name  
Function  
7
S0MODE Serial Port 0 Operation Mode.  
Selects the UART0 Operation Mode.  
0: 8-bit UART with Variable Baud Rate.  
1: 9-bit UART with Variable Baud Rate.  
6
5
UNUSED Unused. Read = 1b, Write = Don’t Care.  
MCE0  
Multiprocessor Communication Enable.  
The function of this bit is dependent on the Serial Port 0 Operation Mode:  
Mode 0: Checks for valid stop bit.  
0: Logic level of stop bit is ignored.  
1: RI0 will only be activated if stop bit is logic level 1.  
Mode 1: Multiprocessor Communications Enable.  
0: Logic level of ninth bit is ignored.  
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.  
4
3
2
1
REN0  
TB80  
RB80  
TI0  
Receive Enable.  
0: UART0 reception disabled.  
1: UART0 reception enabled.  
Ninth Transmission Bit.  
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode  
(Mode 1). Unused in 8-bit mode (Mode 0).  
Ninth Receive Bit.  
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the  
9th data bit in Mode 1.  
Transmit Interrupt Flag.  
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit  
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When  
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0  
interrupt service routine. This bit must be cleared manually by software.  
0
RI0  
Receive Interrupt Flag.  
Set to ‘1’ by hardware when a byte of data has been received by UART0 (set at the  
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to ‘1’  
causes the CPU to vector to the UART0 interrupt service routine. This bit must be  
cleared manually by software.  
Rev. 0.2  
171