C8051F336/7/8/9
Table 21.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A master START was gener- Load slave address + R/W into
1110
0
0
0
0
X
0
0
X
1100
ated.
SMB0DAT.
A master data or address byte Set STA to restart transfer.
1
0
0
1
X
X
1110
-
0 was transmitted; NACK
received.
Abort transfer.
Load next data byte into
SMB0DAT.
0
0
1
1
0
1
1
0
X
X
X
X
1100
End transfer with STOP.
-
-
1100
End transfer with STOP and start
another transfer.
A master data or address byte
1 was transmitted; ACK
received.
0
0
Send repeated START.
1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
0
0
0
0
1
1
1000
1000
Set ACK for next data byte;
Read SMB0DAT.
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DAT.
0
1
0
0
0
0
0
0
X
1000
1110
1100
A master data byte was
received; ACK sent.
0
0
1
Initiate repeated START.
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
1000
Read SMB0DAT; send STOP.
0
1
1
1
1
0
0
0
0
-
Read SMB0DAT; Send STOP
followed by START.
1110
1110
A master data byte was
0 received; NACK sent (last
byte).
0
0
Initiate repeated START.
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
0
0
X
1100
164
Rev. 0.2
SILICON [ SILICON ]
