C8051F360/1/2/3/4/5/6/7/8/9
DATA BUS
ACCUMULATOR
B REGISTER
STACK POINTER
TMP1
TMP2
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
PSW
ALU
DATA BUS
SFR_ADDRESS
SFR_CONTROL
D8
BUFFER
SFR
BUS
INTERFACE
D8
SFR_WRITE_DATA
SFR_READ_DATA
D8
DATA POINTER
PC INCREMENTER
D8
MEM_ADDRESS
MEM_CONTROL
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
PIPELINE
MEMORY
INTERFACE
A16
D8
MEM_WRITE_DATA
MEM_READ_DATA
CONTROL
LOGIC
RESET
CLOCK
SYSTEM_IRQs
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
STOP
IDLE
POWER CONTROL
REGISTER
D8
Figure 9.1. CIP-51 Block Diagram
9.2. Programming and Debugging Support
A C2-based serial interface is provided for in-system programming of the Flash program memory and com-
munication with on-chip debug support logic. The re-programmable Flash can also be read and changed
by the application software using the MOVC and MOVX instructions. This feature allows program memory
to be used for non-volatile data storage as well as updating program code under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints and watch points, starting, stopping and single stepping through program execution (including
interrupt service routines), examination of the program's call stack, and reading/writing the contents of reg-
isters and memory. This method of on-chip debug is completely non-intrusive and non-invasive, requiring
no RAM, Stack, timers, or other on-chip resources.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, macro assembler, debugger and pro-
grammer. The IDE's debugger and programmer interface to the CIP-51 via its C2 interface to provide fast
and efficient in-system device programming and debugging. Third party macro assemblers and C compil-
ers are also available.
Rev. 1.0
81
SILICON [ SILICON ]
