C8051F360/1/2/3/4/5/6/7/8/9
23.2. C2D Port Pin Requirements
Problem
The C2D debugging port pin (shared with P4.6 for C8051F360/3 and P3.0 for C8051F361/2/4/5/6/7/8/9)
behaves differently on "REV A" devices than specified in the data sheet.
On "REV A" devices, a C2D port pin that is pulled low by the associated port pin driver will disrupt debug-
ging capability. In order to communicate with the device through the C2 interface, the value in the port latch
associated C2D port pin must be '1'.
Workaround
To workaround this problem, add a strong pull-up resistor to the C2D port pin to ensure the pin will be high
unless explicitly driven low. Furthermore, the port pin should be left in open-drain mode with a '1' in the
appropriate port latch (PnMDOUT bit = '0', Pn bit = '1') when not in use. This will allow the debugging soft-
ware to transfer data via the C2D pin as often as possible.
This behavior has been corrected on "REV B" of this device.
Rev. 1.0
283
SILICON [ SILICON ]
