C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 21.1. TCON: Timer Control
SFR Page:
SFR Address: 0x88
all pages
(bit addressable)
R/W
R/W
R/W
TF0
Bit5
R/W
TR0
Bit4
R/W
IE1
Bit3
R/W
IT1
Bit2
R/W
IE0
Bit1
R/W
IT0
Bit0
Reset Value
TF1
Bit7
TR1
Bit6
00000000
Bit 7:
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
Bit 6:
Bit 5:
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
Bit 4:
Bit 3:
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External
Interrupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to ‘1’ when /INT1 is active
as defined by bit IN1PL in register IT01CF (see SFR Definition 10.7).
IT1: Interrupt 1 Type Select.
Bit 2:
This bit selects whether the configured /INT1 interrupt will be edge or level sensitive. /INT1
is configured active low or high by the IN1PL bit in the IT01CF register (see SFR Definition
10.7).
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
Bit 1:
Bit 0:
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External
Interrupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to ‘1’ when /INT0 is active
as defined by bit IN0PL in register IT01CF (see SFR Definition 10.7).
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0
is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition
10.7).
0: /INT0 is level triggered.
1: /INT0 is edge triggered.
252
Rev. 1.0
SILICON [ SILICON ]
