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C8051F363 参数 Datasheet PDF下载

C8051F363图片预览
型号: C8051F363
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 288 页 / 2659 K
品牌: SILICON [ SILICON ]
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C8051F360/1/2/3/4/5/6/7/8/9  
SFR Definition 19.1. SCON0: Serial Port 0 Control  
SFR Page:  
SFR Address: 0x98  
all pages  
(bit addressable)  
R/W  
R
R/W  
MCE0  
Bit5  
R/W  
REN0  
Bit4  
R/W  
TB80  
Bit3  
R/W  
RB80  
Bit2  
R/W  
TI0  
Bit1  
R/W  
RI0  
Bit0  
Reset Value  
S0MODE  
01000000  
Bit7  
Bit6  
Bit 7:  
S0MODE: Serial Port 0 Operation Mode.  
This bit selects the UART0 Operation Mode.  
0: 8-bit UART with Variable Baud Rate.  
1: 9-bit UART with Variable Baud Rate.  
UNUSED. Read = 1b. Write = don’t care.  
MCE0: Multiprocessor Communication Enable.  
Bit 6:  
Bit 5:  
The function of this bit is dependent on the Serial Port 0 Operation Mode.  
S0MODE = 0: Checks for valid stop bit.  
0: Logic level of stop bit is ignored.  
1: RI0 will only be activated if stop bit is logic level ‘1’.  
S0MODE = 1: Multiprocessor Communications Enable.  
0: Logic level of ninth bit is ignored.  
1: RI0 is set and an interrupt is generated only when the ninth bit is logic ‘1’.  
REN0: Receive Enable.  
Bit 4:  
This bit enables/disables the UART receiver.  
0: UART0 reception disabled.  
1: UART0 reception enabled.  
Bit 3:  
Bit 2:  
Bit 1:  
TB80: Ninth Transmission Bit.  
The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It  
is not used in 8-bit UART Mode. Set or cleared by software as required.  
RB80: Ninth Receive Bit.  
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th  
data bit in Mode 1.  
TI0: Transmit Interrupt Flag.  
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8-  
bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0  
interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service  
routine. This bit must be cleared manually by software.  
RI0: Receive Interrupt Flag.  
Bit 0:  
Set to ‘1’ by hardware when a byte of data has been received by UART0 (set at the STOP bit  
sampling time). When the UART0 interrupt is enabled, setting this bit to ‘1’ causes the CPU  
to vector to the UART0 interrupt service routine. This bit must be cleared manually by soft-  
ware.  
Rev. 1.0  
225  
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