C8051F124
50 MIPS, 128 kB Flash, 12-Bit ADC, 100-Pin Mixed-Signal MCU
Analog Peripherals
12-Bit ADC
High-Speed 8051 µC Core
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±1 LSB INL; no missing codes
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
±1 LSB INL; no missing codes
Programmable throughput up to 500 ksps
8 external inputs
Programmable amplifier gain: 4, 2, 1, 0.5
Can synchronize outputs to timers for jitter-free waveform generation
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 50 MIPS throughput with 50 MHz system clock
Expanded interrupt handler
8448 bytes data RAM
128 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
are reserved)
External parallel data memory interface
64 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
Programmable 16-bit counter/timer array with six capture/compare
modules
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using a timer or PCA
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
On-chip programmable PLL: up to 50 MHz
External oscillator: Crystal, RC, C, or Clock
Typical operating current: 25 mA at 50 MHz
Typical stop mode current: <0.1 uA
Memory
8-Bit ADC
Digital Peripherals
Two 12-Bit DACs
Two Comparators
Internal Voltage Reference
V
DD
Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
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On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Real-time instruction trace buffer
IEEE1149.1 compliant boundary scan
Clock Sources
Supply Voltage: 2.7 to 3.6 V
100-Pin TQFP
Temperature Range: –40 to +85 °C
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
RST
Digital Power
Analog Power
JTAG
Logic
Boundary Scan
Debug HW
Reset
8
0
5
1
C
o
r
e
SFR Bus
256 Byte
Branch
Target Buffer
Prefetch
HW
32
UART0
UART1
SMBus
SPI Bus
6 Chnl
PCA
Timers
0, 1, 2, 4
Timer 3
P0, P1,
P2, P3
Latches
P0
Drv
P0.0
P0.7
8
MONEN
VDD
Monitor
External
Oscillator
Circuit
Internal
2%
Oscillator
WDT
128 kB
FLASH
256 Byte
RAM
8 kB
XRAM
External Data Memory Bus
C
R
O
S
S
B
A
R
P1
Drv
P1.0/AIN1.0
P1.7/AIN1.7
P2
Drv
P2.0
P2.7
P3
Drv
P3.0
P3.7
XTAL1
XTAL2
System
Clock
VREF1
N/M
PLL
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
ADC
500 ksps
(8-Bit)
Prog
Gain
VREF
VREFD
DAC1
A
M
U
X
8:1
P4.0
Bus Control
DAC0
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
C
T
L
P4 Latch
P4
DRV
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A15
P6.0/A0
P6.7/A7
A
M
U
X
Prog
Gain
ADC
100 ksps
(12-Bit)
Address Bus
A
d
d
r
D
a
t
a
P5 Latch
P6 Latch
P5
DRV
P6
DRV
TEMP
SENSOR
Data Bus
P7 Latch
CP0
CP1
P7
DRV
P7.0/D0
P7.7/D7
Precision Mixed Signal
Copyright © 2004 by Silicon Laboratories
10.6.2004
SILABS [ SILICON LABORATORIES ]
