C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
13.Reset Sources....................................................................................................... 177
13.1.Power-on Reset.............................................................................................. 178
13.2.Power-fail Reset ............................................................................................. 178
13.3.External Reset................................................................................................ 179
13.4.Missing Clock Detector Reset ........................................................................ 179
13.5.Comparator0 Reset ........................................................................................ 179
13.6.External CNVSTR0 Pin Reset........................................................................ 179
13.7.Watchdog Timer Reset................................................................................... 179
13.7.1.Enable/Reset WDT ................................................................................ 180
13.7.2.Disable WDT.......................................................................................... 180
13.7.3.Disable WDT Lockout ............................................................................ 180
13.7.4.Setting WDT Interval.............................................................................. 180
14.Oscillators............................................................................................................. 185
14.1.Internal Calibrated Oscillator .......................................................................... 185
14.2.External Oscillator Drive Circuit...................................................................... 187
14.3.System Clock Selection.................................................................................. 187
14.4.External Crystal Example ............................................................................... 190
14.5.External RC Example ..................................................................................... 190
14.6.External Capacitor Example........................................................................... 190
14.7.Phase-Locked Loop (PLL).............................................................................. 191
14.7.1.PLL Input Clock and Pre-divider ............................................................ 191
14.7.2.PLL Multiplication and Output Clock ...................................................... 191
14.7.3.Powering on and Initializing the PLL...................................................... 192
15.Flash Memory ....................................................................................................... 199
15.1.Programming the Flash Memory .................................................................... 199
15.1.1.Non-volatile Data Storage...................................................................... 200
15.1.2.Erasing Flash Pages From Software ..................................................... 201
15.1.3.Writing Flash Memory From Software.................................................... 202
15.2.Security Options ............................................................................................. 203
15.2.1.Summary of Flash Security Options....................................................... 207
16.Branch Target Cache ........................................................................................... 211
16.1.Cache and Prefetch Operation....................................................................... 211
16.2.Cache and Prefetch Optimization................................................................... 212
17.External Data Memory Interface and On-Chip XRAM........................................ 219
17.1.Accessing XRAM............................................................................................ 219
17.1.1.16-Bit MOVX Example ........................................................................... 219
17.1.2.8-Bit MOVX Example ............................................................................. 219
17.2.Configuring the External Memory Interface.................................................... 219
17.3.Port Selection and Configuration.................................................................... 220
17.4.Multiplexed and Non-multiplexed Selection.................................................... 222
17.4.1.Multiplexed Configuration....................................................................... 222
17.4.2.Non-multiplexed Configuration............................................................... 223
17.5.Memory Mode Selection................................................................................. 224
17.5.1.Internal XRAM Only ............................................................................... 224
17.5.2.Split Mode without Bank Select.............................................................. 224
Rev. 1.4
5
SILICON [ SILICON ]
