Si510/511
Updated Table 2 on page 4.
REVISION HISTORY
Dual CMOS nominal frequency maximum added.
Total stability footnotes clarified for 10 year aging at
40 °C.
Disable time maximum values updated.
Enable time parameter added.
Revision 1.4
June, 2018
Changed “Trays” to “Coil Tape” in the Ordering
Guide.
Updated Table 3 on page 5.
CMOS output rise / fall time typical and maximum
values updated.
LVPECL/HCSL output rise / fall time maximum value
updated.
Revision 1.3
December, 2017
Added new 2.5 x 3.2 mm package options.
LVPECL output swing maximum value updated.
LVDS output common mode typical and maximum
values updated.
Revision 1.2
Updated Table 3.
HCSL output swing maximum value updated.
Duty cycle minimum and maximum values tightened to
48/52%.
Separated LVPECL and HCSL output Rise/Fall time
specs.
Min Rise/Fall times added.
Updated Table 4 on page 6.
Revision 1.1
Phase jitter test condition and maximum value updated.
Phase noise typical values updated.
Updated Table 3.
Additive RMS jitter due to external power supply noise
typical values updated.
Footnote 3 updated limiting the VDD to 2.5/3.3V
CMOS Output Rise/Fall Time Test Condition updated.
Revision 1.0
Added Tables 5, 6, 7 for LVDS, HCSL, CMOS, and
Updated Table 1 on page 3.
Dual CMOS operations.
Updates to supply current typical and maximum values
for CMOS, LVDS, LVPECL and HCSL.
Moved Absolute Maximum Ratings table.
CMOS frequency test condition corrected to 100 MHz.
Updates to OE VIH minimum and VIL maximum values.
Added note to Figure 2 clarifying CMOS and Dual
CMOS maximum frequency.
Updated Figure 10 outline diagram to correct pinout.
30
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 29, 2021
SILICON [ SILICON ]
