Si510/511
REVISION HISTORY
Revision 1.4
June, 2018
Changed “Trays” to “Coil Tape” in the Ordering Guide.
Revision 1.3
December, 2017
Added new 2.5 x 3.2 mm package options.
Revision 1.2
Updated Table 3.
Separated LVPECL and HCSL output Rise/Fall time specs.
Min Rise/Fall times added.
Revision 1.1
Updated Table 3.
CMOS Output Rise/Fall Time Test Condition updated.
Revision 1.0
Updated Table 1 on page 3.
Updates to supply current typical and maximum values for CMOS, LVDS, LVPECL and HCSL.
CMOS frequency test condition corrected to 100 MHz.
Updates to OE VIH minimum and VIL maximum values.
Updated Table 2 on page 4.
Dual CMOS nominal frequency maximum added.
Total stability footnotes clarified for 10 year aging at 40 °C.
Disable time maximum values updated.
Enable time parameter added.
Updated Table 3 on page 5.
CMOS output rise / fall time typical and maximum values updated.
LVPECL/HCSL output rise / fall time maximum value updated.
LVPECL output swing maximum value updated.
LVDS output common mode typical and maximum values updated.
HCSL output swing maximum value updated.
Duty cycle minimum and maximum values tightened to 48/52%.
Updated Table 4 on page 6.
Phase jitter test condition and maximum value updated.
Phase noise typical values updated.
Additive RMS jitter due to external power supply noise typical values updated.
Footnote 3 updated limiting the VDD to 2.5/3.3V
Added Tables 5, 6, 7 for LVDS, HCSL, CMOS, and Dual CMOS operations.
Moved Absolute Maximum Ratings table.
Added note to Figure 2 clarifying CMOS and Dual CMOS maximum frequency.
Updated Figure 10 outline diagram to correct pinout.
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Rev. 1.4
SILICON [ SILICON ]
