Si510/511
CRYSTAL OSCILLATOR (XO) 100 kHZ TO 250 MHZ
Features
Si5602
Supports any frequency from
100 kHz to 250 MHz
Low jitter operation
2 to 4 week lead times
Total stability includes 10-year
aging
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Runt suppression on OE and
power on
Comprehensive production test
2.5x3.2mm
coverage includes crystal ESR and Industry standard 5 x 7, 3.2 x 5,
DLD
and 2.5 x 3.2 mm packages
Pb-free, RoHS compliant
On-chip LDO regulator for power
supply noise filtering
5x7mm and 3.2x5mm
o
–40 to 85 C operation
Ordering Information:
Applications
See page 14.
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
3G-SDI/HD-SDI/SDI
Telecom
Switches/routers
Pin Assignments:
See page 12.
FPGA/ASIC clock generation
Description
The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology
to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO
where a different crystal is required for each output frequency, the Si510/511
uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to
generate any frequency across this range. This IC-based approach allows
the crystal resonator to provide enhanced reliability, improved mechanical
robustness, and excellent stability. In addition, this solution provides superior
supply noise rejection, simplifying low jitter clock generation in noisy
environments. Crystal ESR and DLD are individually production-tested to
guarantee performance and enhance reliability. The Si510/511 is factory-
configurable for a wide variety of user specifications, including frequency,
supply voltage, output format, output enable polarity, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long
lead times and non-recurring engineering charges associated with custom
frequency oscillators.
VDD
1
4
OE
GND
2
3
CLK
Si510 (CMOS)
VDD
1
2
3
6
5
4
NC
OE
CLK–
CLK+
GND
Functional Block Diagram
Si510(LVDS/LVPECL/HCSL/
Dual CMOS)
VDD
V
V
DD
DD
1
1
6
6
OE
OE
Low Noise Regulator
OE
Fixed
Frequency
Oscillator
Any-Frequency
0.1 to 250 MHz
CLK+
CLK–
NC
NC
2
2
5
5
CLK–
CLK–
DSPLL® Synthesis
GND
GND
3
3
4
4
CLK+
CLK+
Si511(LVDS/LVPECL/HCSL/
Dual CMOS)
GND
Rev. 1.4 6/18
Copyright © 2018 by Silicon Laboratories
Si510/511
SILICON [ SILICON ]
