Si500D
Parameters
Condition
LVPECL
Min
—
Typ
34.0
19.3
14.9
25.3
Max
36.0
22.2
16.5
29.3
Units
mA
Low Power LVPECL
LVDS
—
mA
—
mA
HCSL
—
mA
Differential CMOS(3.3 V option,
10 pF on each output, 200 MHz)
—
—
33
16
36
—
mA
mA
Supply Current
Differential CMOS(3.3 V option,
1 pFon each output, 40 MHz)
Differential SSTL-3.3
Differential SSTL-2.5
Differential SSTL-1.8
Tri-State
—
24.5
24.3
22.2
9.7
1.0
—
27.7
26.7
mA
mA
mA
mA
mA
%
—
—
25
—
10.7
Powerdown
—
1.9
Output Symmetry
V
= 0
46 – 13 ns/T
54 + 13 ns/T
460
DIFF
CLK
CLK
LVPECL/LVDS
HCSL/Differential SSTL
Differential CMOS, 15 pF, >80 MHz
Mid-level
—
—
—
—
ps
3
Rise and Fall Times (20/80%)
—
800
ps
1.1
—
1.6
ns
V
– 1.5
V
– 1.34
DD
V
LVPECL Output Option
(DC coupling, 50 to V – 2.0 V)
DD
3
Diff swing
.720
—
.880
V
DD
PK
Low Power LVPECL Output Option
Mid-level
—
N/A
—
V
(AC coupling, 100 Differential
Load)
Diff swing
.68
—
.95
V
3
PK
Mid-level
Diff swing
1.15
0.25
0.85
0.25
0.35
0.65
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.26
0.45
0.96
0.45
0.425
0.82
55
V
LVDS Output Option (2.5/3.3 V)
3
(R
= 100 diff)
V
TERM
PK
Mid-level
V
LVDS Output Option (1.8 V)
3
(R
= 100 diff)
Diff swing
V
TERM
PK
Mid-level
V
3
HCSL Output Option
Diff swing
V
PK
DC termination per pad
V
V
V
, sourcing 9 mA
V
– 0.6
DD
—
OH
3
CMOS Output Voltage
V
, sinking 9 mA
—
0.6
OL
V
V
+ 0.375
—
—
OH
TT
4
4
5
SSTL-1.8 Output Voltage
SSTL-2.5 Output Voltage
SSTL-3.3 Output Voltage
Powerup Time
V
V
V
V
V
– 0.375
—
OL
TT
V
V
+ 0.48
—
OH
TT
V
V
V
– 0.48
—
OL
TT
TT
V
V
+ 0.48
—
OH
TT
V
– 0.48
OL
From time V crosses min spec
DD
—
—
—
—
—
—
—
—
2
ms
ns
ns
µs
supply
OE Deassertion to Clk Stop
250 + 3 x T
250 + 3 x T
CLK
CLK
CLK
Return from Output Driver Stopped
Mode
Return From Tri-State Time
12 + 3 x T
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. VTT = .5 x VDD
.
5. VTT = .45 x VDD
.
2
Rev. 1.1
SILICON [ SILICON ]
