HIGH RIPPLE-REJECTION AND LOW DROPOUT MIDDLE-OUTPUT CURRENT CMOS VOLTAGE REGULATOR
Rev.2.1_00
S-1133 Series
Standard Circuit
INPUT
OUTPUT
VIN
VOUT
*2
*1
CL
ON/OFF
CIN
VSS
GND
Single GND
*1. CIN is a capacitor for stabilizing the input.
A ceramic capacitor of 2.2 µF or more can be used as the output capacitor for
products whose output voltage is 1.7 V or less.
*2. A ceramic capacitor of 1.0 µF or more can be used for CL.
A ceramic capacitor of 2.2 µF or more can be used as the output capacitor for
products whose output voltage is 1.7 V or less.
Figure 17
Caution The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
Application Conditions
Input capacitor (CIN) :
Output capacitor (CL) :
ESR of output capacitor :
1.0 µF or more*1
1.0 µF or more*1
1.0 Ω or less
*1. 2.2 µF or more for products whose output voltage is 1.7 V or less
Caution A general series regulator may oscillate, depending on the external components selected. Check
that no oscillation occurs with the application using the above capacitor.
Selection of Input and Output Capacitors (CIN, CL)
The S-1133 Series requires an output capacitor between the VOUT and VSS pins for phase compensation. Operation is
stabilized by a ceramic capacitor with an output capacitance of 1.0 µF or more*1 in the entire temperature range. However,
when using an OS capacitor, tantalum capacitor, or aluminum electrolytic capacitor, a capacitor with a capacitance of 1.0 µF
or more and an Equivalent Series Resistance (ESR) of 1.0 Ω or less is required.
The value of the output overshoot or undershoot transient response varies depending on the value of the output capacitor.
Perform thorough evaluation using the actual application, including temperature characteristics.
*1. The capacitance is 2.2 µF or more for products whose output voltage is 1.7 V or less.
14
Seiko Instruments Inc.
SII [ SEIKO INSTRUMENTS INC ]
