HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.0_00
S-1112/1122 Series
Operation
1. Basic operation
Figure 12 shows the block diagram of the S-1112/1122 Series.
The error amplifier compares the reference voltage (Vref) with Vfb, which is the output voltage resistance-
divided by feedback resistors Rs and Rf. It supplies the output transistor with the gate voltage necessary
to ensure a certain output voltage free of any fluctuations of input voltage and temperature.
VIN
*1
Current
Error
amplifier
supply
VOUT
−
Vref
Rf
+
Vfb
Reference voltage
circuit
Rs
VSS
Parasitic diode
*1.
Figure 12
2. Output transistor
The S-1112/1122 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due
to inverse current flowing from VOUT pin through a parasitic diode to VIN pin.
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Seiko Instruments Inc.
SII [ SEIKO INSTRUMENTS INC ]
