HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.0_00
S-1112/1122 Series
Standard Circuit
Output
Input
VIN
VOUT
*2
*1
ON/OFF
CL
CIN
VSS
GND
Single GND
*1. CIN is a capacitor for stabilizing the input.
*2. A ceramic capacitor of 0.47 µF or more can be used for CL.
Figure 10
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
Application Conditions
Input capacitor (CIN):
Output capacitor (CL):
ESR of output capacitor:
1.0 µF or more
0.47 µF or more
10 Ω or less
Caution A general series regulator may oscillate, depending on the external components selected.
Check that no oscillation occurs with the application using the above capacitor.
Seiko Instruments Inc.
11
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