BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-1004 Series
Rev.2.1_01
17. Release delay time (tRESET
)
vs. Power supply voltage (VDD)
S-1004Cx10
Ta = +25°C,
CD = 4.7 nF
16
15
14
13
12
11
0.0
2.0
4.0
6.0
8.0
10.0
VDD [V]
1 s
*1
IH
V
SENSE pin voltage
*2
V
IL
tRESET
V
DD
V
DD 90%
Output voltage
V
SS
*1. VIH = 10 V
*2. VIL = 0.95 V
Figure 36 Test Condition of Release Delay Time
R
VDD
VDD
100 kΩ
VDD
VDD
Oscilloscope
Oscilloscope
OUT
OUT
SENSE
SENSE
P.G.
P.G.
VSS CD
VSS CD
CD
CD
Figure 37 Test Circuit of Release Delay Time
(Nch open-drain output product)
Figure 38 Test Circuit of Release Delay Time
(CMOS output product)
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
32
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